A Software-Defined Radio Receiver in 65nm CMOS Robust to Out-of-Band Interference

Two techniques are presented in this paper for a software-defined radio (SDR) receiver robust to out-of-band interference. Voltage gain is realized at IF simultaneously with low-pass filtering to mitigate blockers and out-of-band intermodulation distortion. A 2-stage polyphase harmonic rejection (HR) mixer concept robust to gain error achieves 2nd-6th HR of more than 60dB for 40 samples without trimming or calibration. A prototype 0.4-0.9G zero-IF receiver in 65nm CMOS has 34dB gain, 4dB NF, +3.5dBm IIP3 and +47dBm IIP2 while drawing 50mA from 1.2V

A Polyphase Multipath Technique for Software-Defined Radio Transmitters

Transmitter circuits using large signal swings and hard-switched mixers are power-efficient, but also produce unwanted harmonics and sidebands, which are commonly removed using dedicated filters. This paper presents a polyphase multipath technique to relax or eliminate filters by canceling a multitude of harmonics and sidebands. Using this technique, a wideband and flexible power upconverter with a clean output spectrum is realized in 0.13-mum CMOS, aiming at a software-defined radio application. Prototype chips operate from DC to 2.4 GHz with spurs smaller than -40 dBc up to the 17th harmonic (18-path mode) or 5th harmonic (6-path mode) of the transmit frequency, without tuning or calibration. The transmitter delivers 8 mW of power to a 100-Omega load (2.54 Vpp-diff voltage swing) and the complete chip consumes 228 mW from a 1.2-V supply. It uses no filters, but only digital circuits and mixer

Multipath Polyphase Circuits and their Application to RF Transceivers

Nonlinearity and time-variance in radio frequency (RF) circuits leads to unwanted harmonics and intermodulation products, e.g. in power amplifiers and mixers. This paper reviews a recently proposed multipath polyphase circuit technique which can cancel such harmonics and intermodulation products. This will be illustrated using a power upconverter IC as an example. The upconverter works from DC to 2.4 GHz, and the multipath polyphase technique cleans its spectrum up to the 17th harmonic, keeping unwanted spurious responses more than 40dB below the carrier. The technique can also be useful for other applications, and some possible applications will be discussed

A flicker noise/IM3 cancellation technique for active mixer using negative impedance

This paper presents an approach to simultaneously cancel flicker noise and IM3 in Gilbert-type mixers, utilizing negative impedances. For proof of concept, two prototype double-balanced mixers in 0.16- m CMOS are fabricated. The first demonstration mixer chip was optimized for full IM3 cancellation and partial flicker noise cancellation; this chip achieves 9-dB flicker noise suppression, improvements of 10 dB for IIP3, 5 dB for conversion gain, and 1 dB for input P1 dB while the thermal noise increased by 0.1 dB. The negative impedance increases the power consumption for the mixer by 16% and increases the die area by 8% (46 28 m ). A second demonstration mixer chip aims at full flicker noise cancellation and partial IM3 cancellation, while operating on a low supply voltage ( 0.67 x Vdd; in this chip,the negative impedance increases the power consumption by 7.3% and increases the die area by 7% (50 20 m ). For one chip sample, measurements show 10-dB flicker noise suppression within 200% variation of the negative impedance bias current; for ten randomly selected chip samples, 11-dB flicker noise suppression is measured

A CMOS spectrum analyzer frontend for cognitive radio achieving +25dBm IIP3 and −169 dBm/Hz DANL

A dual RF-receiver preceded by discrete-step attenuators is implemented in 65nm CMOS and operates from 0.3– 1.0 GHz. The noise of the receivers is reduced by cross-correlating the two receiver outputs in the digital baseband, allowing attenuation of the RF input signal to increase linearity. With this technique a displayed average noise level below -169 dBm/Hz is obtained with +25 dBm IIP3, giving a spurious-free dynamic range of 89 dB in 1 MHz resolution bandwidth

Organic chicken product authentication: state-of-the-art and future perspectives

Podeu consultar el llibre complet a: http://hdl.handle.net/2445/63704Organic food products are highly susceptible to fraud. Currently, administrative controls are conducted to detect fraud, but having an analytical tool able to verify the organic identity of food would be very supportive. The state-of-the-art in food authentication relies on fingerprinting approaches that find characteristic analytical patterns to unequivocally identify authentic products. While wide research on authentication has been conducted for other commodities, the authentication of organic chicken products is still in its infancy. Challenges include finding fingerprints to discriminate organic from conventional products, and recruiting sample sets that cover natural variability. Future research might be oriented towards developing new authentication models for organic feed, eggs and chicken meat, keeping models updated and implementing them into regulations. Meanwhile, these models might be very supportive to the administrative controls directing inspections towards suspicious fraudulent samples

A 1 Volt switched transconductor mixer in 0.18 μm CMOS

A new CMOS mixer topology can operate at low supply voltages by using switches connected only to the supplies. Mixing is achieved exploiting two cross-coupled transconductors, which are alternatingly activated by the switches. A down conversion mixer prototype with 12 dB conversion gain was designed and realized in standard 0.18 μm CMOS. It achieves satisfactory mixer performance up to 4 GHz, at a supply voltage of 1 Volt. Moreover, the mixer topology features a fundamental high frequency noise figure benefit

A 100 – 800MHz 8-Path polyphase transmitter with mixer duty-cycle control achieving

Radio transceivers capable of dynamic spectrum access require frequency agile transmitters with a clean output spectrum. High-Q filters are difficult to implement on chip and have limited tuning range. Transmitters with high linearity and broadband harmonic rejection can be more flexible and require less filtering. However, traditional Harmonic Rejection mixers suppress only a few harmonics. This paper presents an 8-path poly-phase transmitter, which exploits mixer-LO duty-cycle control and a tunable first-order RC low-pass filter to suppress ALL harmonics to below -40dBc. The optimum duty-cycle theoretically is 43.65% and a resolution of better than 0.1% is required to keep the spread in harmonic rejection within 1dB. We propose a simple monotonic duty-cycle control circuit and show by design equations and measurements that it achieves the required resolution over 3 octaves of frequency range. Also, analysis indicates that LO duty-cycle reduction compared to 50% improves power upconverter efficiency. A transmitter realized in 0.16￭m CMOS works from 100-800MHz at a maximum single tone output power of 10.8dBm with an efficiency of 8.7%, outperforming previous designs. The OIP3 is >21dBm, while the LO leakage and image rejection is better than -45dBc